A. Field of the Invention
The present invention relates to a high voltage and high current capacity semiconductor device applicable to MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), bipolar transistors, diodes and the like. The invention also relates to a method of manufacturing such a semiconductor device.
B. Description of the Related Art
Semiconductor devices are generally classified into lateral semiconductor devices and vertical semiconductor devices. The former have electrodes on one surface of the semiconductor substrate and the main electric current flows along a principal surface. The latter have electrodes on the both surfaces and the main current flows between the electrodes on the both principal surfaces. In the vertical semiconductor device, the direction of the drift current flowing in the ON state is the same as the direction of depletion layer expansion due to a reverse biased voltage in the OFF state. In a conventional planar n channel vertical MOSFET, the high resistivity n-drift layer carries the drift current in the vertical direction in the ON state of the MOSFET, and is depleted in the OFF state to hold a breakdown voltage. Reducing a thickness of the high resistivity n-drift layer, that is, reducing the current path in the n-drift layer, leads to an effect of substantial ON resistance reduction of the MOSFET owing to the decreased resistance in the drift layer. Such a configuration, however, results in a narrowed width of the depletion layer that expands from a pn junction between the p base region and the n drift layer. Consequently, the electric field strength soon reaches the critical value of silicon, decreasing a breakdown voltage. On the other hand, a semiconductor device exhibiting a high breakdown voltage has a thick n-drift layer and causes a high ON resistance, which leads to an increased loss. This relationship between the ON resistance and the breakdown voltage is called a trade-off relationship. This trade-off relationship exists in semiconductor devices such as IGBTs, bipolar transistors, diodes and the like as well.
Meanwhile, in order to achieve a high breakdown voltage in a vertical semiconductor device, the device needs a peripheral region in a ring shape surrounding the active region in which the main current flows. The peripheral region is, from a viewpoint of a main current path, an inactive region, and is desired to be as narrow as possible from a viewpoint of effective use of semiconductor material. Concerning this point, Japanese Unexamined Patent Application Publication No. 2008-193043 (FIG. 5-1 and FIG. 5-2, in particular) discloses a technique in which a peripheral region comprises a plurality of p-type guard rings, first field plates composed of polysilicon, and second field plates composed of a metal film. In the structure of JP2008-193043, a contact hole for establishing the same potential value between the guard ring and the field plate is formed in the corner section of the peripheral region. As a result, a width of the straight section of the peripheral region is narrowed and the area for the active region is expanded.
A different technique concerning a peripheral region in a semiconductor device is disclosed in Japanese Unexamined Patent Application Publication No. 2009-117715 (Abstract, FIG. 1, and FIG. 3, in particular), in which a plurality of guard rings and field plates are formed in the peripheral region. The field plates of polysilicon are disposed on the surface of each guard ring at the inner and outer circumferential sides through an insulator film. A metal electrode is provided for electrically connecting the guard ring and the field plate. This structure makes it possible to narrow the gap between the field plates.
Although the MOSFET disclosed in JP2008-193043 attains high relaxation of electric field and high robustness against induces charges with a narrow width in a peripheral region, the p-type guard rings need to be formed before forming the polysilicon field plates. In case that p-type guard rings are formed after forming the polysilicon gate and polysilicon field plates, additional steps of photolithography and ion implantation are needed to form the p-type guard rings. These additional steps not only raise manufacturing costs, but also tend to create misalignment between the p-type guard ring and the polysilicon field plate, which may degrade the electric field relaxation performance and the robustness against induced charges.
JP2009-117715 discloses a device in which a region for connecting a p-type guard ring and a polysilicon field plate is formed in a ring shape, and the region for connecting the p-type guard ring and the polysilicon field plate is provided in a straight section of the peripheral region. Thus, the width in the peripheral region is relatively large.
The p-type guard ring in the JP2009-117715 is formed before forming the field plate as in the device of JP2008-193043. Therefore, the device of JP2009-117715 has the same problems as the device of JP2008-193043 mentioned above.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.